8101 Datasheet, PDF (159/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

Figure 6.10 Register Interface Timing, Counter Read Cycle (of the Same Counter)
REGCLK
1
2
6
1
3
t₈₁
t₈₂
REGCSn
REGWRn
t₈₁
REGRDn
REGAD[15:0]
REGD[15:0] _High-Z
t₈₁
1st Counter Address
t₈₃
t₈₄
Not Valid
t₈₄
2nd Counter Address
1st 16 Bits of
Counter Result
t₈₃
t₈₄
Not Valid
t₈₂
t₈₄
2nd 16 Bits of
Counter Result
High-Z
AC Electrical Characteristics
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