8101 Datasheet, PDF (86/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

TX[9:0]
Transmit Data
Output
These interface outputs transmit data on the rising edge
of TBC.
3.3 Register Interface Signals
This section describes the 8101/8104 register interface signals.
REGA[7:0]
Register Interface Address
Input
These inputs provide the address for the specific internal
register to be accessed, and are clocked into the device
on the rising edge of REGCLK.
REGCLK
Register Interface Clock
Input
This input clocks data in and out on REGD[15:0],
REGA[7:0], REGRDn, and REGWRn on its rising edge.
REGCLK frequency must be between 5–40 MHz.
REGCSn
Register Interface Chip Select
Input
This input must be asserted to enable reading and writing
data on REGD[15:0] and REGA[7:0]. This input is
clocked in on the rising edge of REGCLK.
REGD[15:0]
Register Interface Data Bus
Bidirectional
This bus is a bidirectional 16-bit data path to and from the
internal registers. Data is read and written from and to
the internal registers on the rising edge of the register
clock, REGCLK.
REGINT
Register Interface Interrupt
Output
This output is asserted when certain interrupt bits in the
registers are set, and it remains latched HIGH until all
interrupt bits are read and cleared.
REGRDn
Register Interface Read
Input
When this input is asserted, the accessed internal
register is read (data is output from the register). This
input is clocked into the device on the rising edge of
REGCLK.
REGWRn
Register Interface Write
Input
When this input is asserted, the accessed internal
register is written (data is input to the register). This input
is clocked into the device on the rising edge of REGCLK.
3-8
Signal Descriptions
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