8101 Datasheet, PDF (117/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

MCFLTR
MAC Control Frame Address Filter Enable 12, R/W
MCFLTR
Description
1
Use reserved multicast address or station
address as the DA to determine MAC control
pause frame validity
0
Use any address as the DA to determine MAC
control pause frame validity
MCENDPS
MAC Control Frame End Pause Enable
11, R/W
MCENDPS Description
1
When FNCTRL is deasserted, send transmit
MAC control frame with pause_time = 0
0
Normal
MCASND[3:0]
MAC Control Frame AutoSend
Threshold
[10:7], R/W
These bits determine the receive FIFO threshold, which
causes the automatic transmission of pause frames.
Autogenerated pause frame transmission is also affected
by the FCNTRL pin and bit 1.
MCASND[3:0]
1111
Description
15360 bytes
0010
0001
0000
2048 bytes
1024 bytes
Disabled, i.e. RX FIFO data does not cause
autogenerated pause frame transmission.
RES
Reserved
[6:0], R/W
Must be left at defaults or written to 0 for proper
operation.
4.3.17 Register 20–Flow Control 2
15
0
P[15:0]
Note: P15 15-bit occurs on REGD15 pin
Register Definitions
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved.
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