8101 Datasheet, PDF (110/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

FCNTRL_DIS FCNTRL Pin
1, R/W
FCNTRL_DIS Description
1
FCNTRL pin disabled (does not cause
autogenerated pause frame transmission).
0
Enabled
SD_EN
Signal Detect Pin Enable
0, R/W
SD_EN Description
1
Enabled
0
SD pin disabled, i.e., internal SD always asserted,
does not affect receive word synchronization
4.3.11 Register 10–Configuration 4
15
14
13
12
11
10
98
7
6
5
0
ENDIAN BUSSIZE RES LPBK LNKDN TBC_DIS RES CMXPKT1 CMXPKT0
RES
Note: ENDIAN 15-bit occurs on the REGD15 pin
ENDIAN
Endian Select
15, R/W
ENDIAN
Description
1
RXD/TXD data in big endian format
0
RXD/TXD data in little endian format
BUSSIZE
Bus Size Word Width
14, R/W
BUSSIZE
Description
1
Receive system bus word width is 16 bits
0
Receive system bus word width is 32 bits
RES
Reserved
13, [9:8], [5:0], R/W
Must be left at default value or written to 0 for proper
device operation.
LPBK
Loopback Enable
LPBK
1
0
Description
Loopback mode enabled
Normal
12, R/W
4-22
Registers
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