8101 Datasheet, PDF (74/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

Table 2.14 Counter Definition (Cont.)
Counter Description
Counter Counter Name
Number (MIB Object Name)
RX/TX Definition
Size
(Bits)
Register
Address
REGAD[7:0]
(Low/High)
49
aSQETestErrors
Number of times SQE was asserted.
RX
Equivalent to "dot3StatsSQETestError" 32
Use Ctr. #40
aSymbolErrorDuringCarrier
One or more symbol errors received
from a PHY during packet reception,
exclusive of collision. This counter is
only incremented once per packet,
regardless of the number
RX
of symbol errors in that packet.
0b11100010
0b11100011
aMACControlFramesTransmitted
TX
Valid MAC Control packets.
Equivalent to
"apauseMACCtrlFramesTransmitted"
Use Ctr. #52
Valid MAC Control packets.
Equivalent to
50
aMACControlFramesReceived
RX
"apauseMACCtrlFramesReceived"
32
Use Ctr. #53
Valid MAC Control packets
51
aUnsupportedOpcodesReceived
RX
with non-pause opcode.
0b11100100
32
0b11100101
Valid MAC Control packets
52
apauseMACCtrlFramesTransmitted TX
with pause opcode.
0b11100110
32
0b11100111
Valid MAC Control packets
53
apauseMACCtrlFramesReceived
RX
with pause opcode.
0b11101000
32
0b11101001
1. Footnotes
a. Bad RX packet = legal-length error, CRC error, receive FIFO overflow, symbol error.
Where: CRC Error is bad FCS with an integral number of octets. Alignment Error is bad FCS with
nonintegral number of octets. Symbol Error is an invalid codeword or a /V/.
b. Bad TX packet = legal-length error, transmit FIFO underflow.
c. Legal-length packet is between 64 and Max_Packet_Length in bytes. Preamble is not included
in length count.
d. Max_Packet_Length for the counters can be programmed to be either 1518, 1522, 1535, or
unlimited bytes. 1518 is the default for both transmit and receive.
e. The counter result is stored in two 16-bit registers. Thus, there are two register addresses for
each counter. Of the two registers for a given counter, the register with the lower value address
contains the least significant counter bits.
f. The RMON specs explicitly states that packet and octet counters should only tabulate received
information. This is sometimes interpreted to mean both transmitted and received information
because Ethernet was originally a shared media. As such, transmit packet and octet counters are
also available in counters 18–27 and can be summed with receive packet and octet counts if
desired.
2-56
Functional Description
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