8101 Datasheet, PDF (42/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

2.9.5 Link Down FIFO Flush
When the link is down (also referred to as link fail) and defined by either
receiver has lost sync or AutoNegotiation process has not yet completed,
the transmitter at the 10-bit PHY interface is occupied with sending either
idle or AutoNegotiation codes (/I/ or /C/ see Table 2.8). As a result, data
cannot exit the transmit FIFO to the transmit MAC section. If data
continues to be input to the transmit FIFO from the system interface
while the controller is in the link fail mode the transmit FIFO may
overflow. Enabling the link down FIFO flush feature causes the data
exiting the transmit FIFO to be automatically discarded when the
controller is in the link fail mode, thus preventing any possible overflow
of the transmit FIFO. Setting the Link Down FIFO Flush Enable bit
(LNKDN) in “Register 10–Configuration 4‚" Section 4.3.11, enables the
link down FIFO flush mode.
2.10 Receive FIFO
The receive FIFO acts as a temporary buffer between the receive MAC
section and system interface. The receive FIFO size is 16 Kbytes. Data
is clocked into the receive FIFO with the 125 MHz 8B10B PCS clock.
Data is clocked out of the receive FIFO with the 33−66 MHz system
interface clock, SCLK. There are two programmable watermark outputs,
RXWM1 and RXWM2, which aid in managing the data flow out of the
receive FIFO.
2.10.1 Watermarks
There are two watermarks for the receive FIFO. which are output on the
RXWM1 and RXWM2 pins. These watermarks are asserted when the
receive FIFO data exceeds the thresholds associated with the
watermarks.
The receive watermark thresholds for RXWM1 and RXWM2 can be
programmed over the entire 16 Kbyte receive FIFO range. Each of the
watermark thresholds is independently programmed with eight bits that
reside in the Receive FIFO Threshold register. Whenever the data in the
FIFO exceeds the threshold of either watermark, the respective
watermark pin on either RXWM1 or RXWM2 is asserted HIGH. RXWM2
is also asserted if a complete packet is loaded into the receive FIFO from
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Functional Description
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