8101 Datasheet, PDF (24/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

2.3 Receive Data Path
The 10-bit PHY interface receives incoming encoded data from an
external PHY device. The incoming encoded data must be encoded in
the 10-bit PHY format specified in IEEE 802.3z, as shown in Figure 2.3.
The incoming encoded data is then sent to the receive 8B10B PCS
block, which strips off the framing delimiters, decodes the data, and
converts the encoded data into an Ethernet packet according to the
IEEE 802.3 specifications, as shown in Figure 2.2. The Ethernet packet
data is then sent to the receive MAC section.
The receive MAC section disassembles the packet, checks the validity of
the packet against certain error criteria and address filters, and checks
for MAC control frames. The receive MAC then sends valid packets to
the receive FIFO. The receive FIFO provides temporary storage of data
until it is demanded by the system interface. The system interface
outputs the data to an external bus.
2.4 Register Structure
The controller has 136 internal 16-bit registers. 22 registers are available
for setting configuration inputs and reading status outputs. The remaining
114 registers are associated with the management counters.
The register interface is a separate internal register bidirectional 16 bit
data bus to set configuration inputs, read status outputs, and access
management counters.
The location of all registers is described in the Register Addressing Table
in Section 4.2, “Register Addresses”. The description of each bit for each
register is described in Section 4.3.1 through Section 4.3.25.
2.5 Ethernet Frame Format
Information in an Ethernet network is transmitted and received in packets
or frames. The basic function of the controller is to process Ethernet
frames. An Ethernet frame is defined in IEEE 802.3 and consists of a
preamble, start of frame delimiter (SFD), destination address (DA),
2-6
Functional Description
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