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8101 Datasheet, PDF (36/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller | |||
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2.8.3 Unicast Address Filter
Comparing the destination address of the receive packet against the
48-bit value stored in the three MAC Address registers (registers 0, 1
and 2) ï¬lters unicast packets. When the destination address of a unicast
packet matches the value stored in these registers the unicast packet is
deemed valid and passed to the receive FIFO; otherwise, the packet is
rejected. The correspondence between the bits in the MAC Address
registers and the incoming bits in the destination address of the receive
packet is deï¬ned in the MAC Address register deï¬nitions.
To program the controller to always reject unicast packets, set the
REJUCST bit in âRegister 8âConï¬guration 2â" Section 4.3.9. When this
bit is set all unicast packets are rejected regardless of their address.
Unicast packet address ï¬ltering functions do not affect the reception of
MAC control frames. Other bits described in Section 2.17, âMAC Control
Frames,â control the reception of MAC control frames.
2.8.4 Multicast Address Filter
The multicast address ï¬lter function computes the CRC on the incoming
Destination Address and produces a 6-bit number that is compared
against the 64 values stored in the MAC Address Filter 1â4 registers
(Registers 3, 4, 5, and 6). When the multicast packet destination address
passes the address ï¬lter, the packet is deemed valid and passed to the
receive FIFO; otherwise, the packet is rejected.
The multicast address ï¬lter requires 64 address ï¬lter bits to be written
into the Address Filter 1â4 registers. The multicast address ï¬ltering
algorithm is as follows:
1. Compute a separate 32-bit CRC on the destination address ï¬eld
using the same IEEE 802.3 deï¬ned method that computes the
transmit CRC.
2. Use bits [0:2] of the destination address FCS to select one of the
bytes in the 64-bit address ï¬lter, as shown in Table 2.5.
3. Use bits [3:5] of the destination address FCS to select one of the bits
within the byte selected in (2), as shown in Table 2.5.
2-18
Functional Description
Copyright © 2000â2001 by LSI Logic Corporation. All rights reserved.
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