8101 Datasheet, PDF (85/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

3.2 10-Bit PHY Interface Signals
This section describes the 8101/8104 10-Bit PHY interface signals.
EN_CDET
Comma Detect Enable
Output
This output is asserted when either the receive 8B10B
PCS state machine is in the loss of synchronization state
or the CDET bit is set in “Register 9–Configuration 3‚"
Section 4.3.10. This output is typically used to enable the
comma detect function in an external physical layer
device.
EWRAP
Loopback Output Enable
Output
This output is asserted whenever the EWRAP bit is set
in “Register 9–Configuration 3‚" Section 4.3.10. This
output is typically used to enable loopback in an external
physical layer device.
LCK_REFn
Receiver Lock
Output
This output is asserted whenever the LCK_REFn bit is
set in “Register 9–Configuration 3‚" Section 4.3.10. This
output is typically used to enable the receive
lock-to-reference mechanism in an external physical
layer.
RBC[1:0]
Receive Clock
Input
The RBC[1:0] signals clock receive data into the
controller on the clock rising edge. RBC[1:0] are
62.5 MHz clocks, 180° out of phase, that clock data into
the controller on RX[9:0] at an effective rate of 125 MHz.
For the device to acquire synchronization, the comma
code must be input on RXD[9:0] on RBC1 rising edges.
RX[9:0]
Receive Data
Input
These inputs contain receive data that are clocked in on
the rising edges of RBC[1:0].
TBC
Transmit Clock
Output
This output clock transmits data out on TX[0:9] on its
rising edge. TBC is a 125 MHz clock and is generated
from TCLK.
10-Bit PHY Interface Signals
3-7
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