8101 Datasheet, PDF (28/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

transmit system interface inputs. When TXENn is asserted, a data word
on the TXD[31:0] input is clocked into the transmit FIFO on each rising
edge of the SCLK clock input. Multiple packets may be clocked in on one
TXENn assertion. The TXD[31:0] input data is a 32-bit wide packet data
whose format and relationship to the MAC packet and 10-bit PHY data
is described in Figure 2.3.
The TXBE[3:0] pins determine which bytes of the 32-bit TXD[31:0] data
word contain valid data. TXBE[3:0] are clocked in on the rising edge of
SCLK along with each TXD[31:0] data word. The correspondence
between the byte enable inputs and the valid bytes of each data word on
TXD[31:0] is defined in Table 2.2. Any logic combination of TXBE[3:0]
inputs is allowed, with the one exception that TXBE[3:0] must not be
0b0000 on the SCLK cycle when TXSOF or TXEOF is asserted.
Table 2.2 Byte Enable Pin vs. Valid Byte Position
TXBE[3:0]/RXBE[3:0] Byte
Valid Bytes on
Enable Pins
TXD[31:0]/RXD[31:0] Pins
TXBE[3]/RXBE[3] Asserted
TXBE[2]/RXBE[2] Asserted
TXBE[1]/RXBE[1] Asserted
TXBE[0]/RXBE[0] Asserted
TXD[31:24]/RXD[31:24]
TXD[23:16]/RXD[23:16]
TXD[15:8]/RXD[15:8]
TXD[7:0]/RXD[7:0]
The TXSOF and TXEOF signals indicate to the controller which data
words start and end the Ethernet data packet, respectively. These
signals are input on the same SCLK rising edge as the first and last word
of the data packet.
The TXWM1n and TXWM2n signals indicate when the transmit FIFO has
exceeded the programmable watermark thresholds. The controller
asserts the watermarks on the rising edge of SCLK, depending on the
fullness of the transmit FIFO. Refer to Section 2.9, “Transmit FIFO,” for
more details on these watermarks.
2-10
Functional Description
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