8101 Datasheet, PDF (29/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

TXDC is a transmit packet discard output. TXDC is asserted every time
the transmission of the packet being input on the system interface was
halted and the packet discarded due to some error. This signal is latched
HIGH. It is cleared when the clearing signal, CLR_TXDC, is asserted or
cleared automatically if the controller is placed in the AutoClear mode.
See Section 2.13, “Packet Discard,” for more details on discards and
TXDC.
TXCRCn is an input that can enable the internal generation and
appending of the 4-byte CRC value onto the end of the data packet.
TXCRCn is sampled on the rising edge of SCLK and has to be asserted
at the beginning of the packet, coincident with TXSOF, to remove or add
the CRC to that packet. Setting the transmit CRC enable bit (TXCRC) in
the Configuration 1 register also enables CRC generation. Refer to
Section 2.7.3, “CRC Generation” for more details on CRC generation and
the interaction between TXCRCn and the TXCRC bit.
FCNTRL is an input that causes the automatic generation and
transmission of a MAC control pause frame. FCNTRL is input on the
rising edge of SCLK. See Section 2.17, “MAC Control Frames,” for more
details about this feature.
2.6.3 Receive Timing
The receive portion of the system interface consists of 45 signals:
• 32 receive output data bits (RXD[31:0])
• One receive enable input (RXENn)
• Four receive byte enable outputs (RXBE[3:0])
• One receive start of frame and one end of frame outputs (RXSOF
and RXEOF)
• Two receive FIFO watermark outputs (RXWM1 and RXWM2)
• One receive discard output (RXDC)
• One receive discard clear input (CLR_RXDC)
• One receive packet abort input (RXABORT)
• One receive output enable (RXOEn)
All receive and transmit data is clocked in and out with the system clock,
SCLK, which must operate between 33–66 MHz.
System Interface
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved.
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