8101 Datasheet, PDF (87/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

3.4 Micellaneous Signals
This section describes the 8101/8104 micellaneous signals.
LINKn
Receive Link
Output
When this signal is HGH, there is no link. When this
signal is asserted, the receive link is synchronized and
configured.
RESERVED Reserved
These pins are reserved and must be left floating.
RESETn
Reset
Input
When this signal is HIGH, controller is in normal
operation. When this signal is asserted, controller resets,
FIFO’s are cleared, counters are cleared, and register
bits are set to default values.
SD
Signal Detect
Input
When this signal is asserted, data detected on receive
10-bit PHY is valid. When SD is LOW, data is not valid
and the 8B10B PCS receiver is forced to a loss of sync
state. This signal is ignored (assumed high) unless the
SD_EN bit in “Register 9–Configuration 3‚"
Section 4.3.10, is cleared.
TAP
3-state all pins
Input
This pin is used for testing purposes only. When
asserted, all output and bidirectional pins are placed in a
high-impedence state.
TEST
Test Mode
Input
This pin is used for factory test and must be tied LOW for
proper operation.
TCLK
Transmit Clock
Input
This 125 MHz input clock is used by the 8B10B PCS
section and generates the 125 MHz transmit output clock,
TBC, is used to output data on the 10-bit PHY interface.
Micellaneous Signals
3-9
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