8101 Datasheet, PDF (75/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

2.19.1 Counter Half Full
Each 32-bit counter has a half-full status output bit associated with it.
The half-full bits are stored in “Register 112–115–Counter Half Full 1-4‚"
Section 4.3.23. A half-full bit is set when its counter value reaches
0x80000000 (MSB bit goes from a 0 to a 1), so it is set when the counter
becomes half full.
The counter half-full bits latch themselves when they are set. Each bit
stays latched until either the bit is read or the counter register with which
the bit is associated is read. Counter half-full bits are also interrupt bits
(the setting of any counter half-full bit can be programmed to cause the
assertion of the interrupt pin, REGINT). When a read clears the counter
half-full bit, the interrupt is also cleared.
Note: REGINT stays asserted until all interrupt bits are cleared.
Each counter half-full bit can be individually programmed to assert (or
not assert) the REGINT pin. Setting the appropriate mask bit associated
with the counter half full “Registers 120–123–Counter Half Full Mask 1-
4‚" Section 4.3.24, programs the controller to mask (disable) the interrupt
caused by the corresponding counter half full detect bit.
2.19.2 Counter Reset On Read
A read operation on a counter does not normally affect the counter
values. However, setting the CTR_RD bit in “Register 9–Configuration 3‚"
Section 4.3.10, programs the counter to automatically reset to zero when
read.
When the CTR_RD bit is set, a counter is cleared to 0 whenever any one
of the two 16-bit counter registers associated with a 32-bit counter is
read. An internal holding register stores the entire 32-bit counter result
so that the result is correctly read as long as two successive 16-bit
counter register reads are performed from the same counter. In order to
read the cleared value, the read operation needs to be deasserted then
reasserted (i.e., REGCSn and REGRDn).
When the CTR_RD bit is cleared (default), a read does not affect the
count in the counter, as long as the counter is not at maximum count. If
a counter is at maximum count, its count is always reset to 0 when the
counter is read.
Counters
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