8101 Datasheet, PDF (7/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

Contents
CChapter 1
Chapter 2
Introduction
1.1 Overview
1.2 Features
Functional Description
2.1 Overview
2.2 Transmit Data Path
2.3 Receive Data Path
2.4 Register Structure
2.5 Ethernet Frame Format
2.5.1 Preamble and SFD
2.5.2 Destination Address
2.5.3 Source Address
2.5.4 Length/Type Field
2.5.5 Data
2.5.6 Frame Check Sequence (FCS)
2.5.7 Interpacket Gap (IPG)
2.6 System Interface
2.6.1 Data Format and Bit Order
2.6.2 Transmit Timing
2.6.3 Receive Timing
2.6.4 Bus Width
2.6.5 System Interface Disable
2.7 Transmit MAC
2.7.1 Preamble and SFD Generation
2.7.2 AutoPad
2.7.3 CRC Generation
2.7.4 Interpacket Gap
2.7.5 MAC Control Frame Generation
8101/8104 Gigabit Ethernet Controller
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved.
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