8101 Datasheet, PDF (91/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

Table 4.1 Register Bit Type Definition
Bit Types
Definition
Symbol Name
Write Cycle
Read Cycle
W
Write
Input
No operation, output not valid
R
Read
No operation, input ignored Output
R/W
Read/Write
Input
Ouput
R/W
Read/Write
Input
Ouput
SC
Self Clearing
Clears itself after operation
completed
R/LL
Read, Latch when 0 No operation latching
Output
R/LLI
Read, Latch when
0, Assert Interrupt
Input ignored when bit goes to 0,
bit latched, and interrupt asserted
(if not masked)
When bit is read, bit updated and
interrupt cleared
R/LH
Read/write
No operation, input ignored Output
R/LHI
Read/write, latch
HIGH with interrupt
When bit goes to 1, bit latched &
interrupt asserted (if not masked)
When bit is read, bit updated and
interrupt cleared
R/LT
R/LTI
Read, Latch on
Transition
Read, Latch on
Transition with
interrupt
No operation, input ignored Output
When bit transitions, bit latched and
interrupt asserted (if not masked)
When bit is read, bit updated and
interrupt cleared
4.1.2 Interrupt
An interrupt is triggered when certain output status bits change state.
These bits are called interrupt bits and are designated as R/LLI, R/LHI,
and R/LTI bits, as described in the previous section. The interrupt bits
reside in “Register 11–Status 1‚" Section 4.3.12, and “Register 112–115–
Counter Half Full 1-4‚" Section 4.3.23,. Interrupt bits automatically latch
Register Interface
4-3
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