8101 Datasheet, PDF (10/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

Chapter 4
x
3.5 Power Supply Signals
3-10
Registers
4.1 Register Interface
4.1.1 Bit Types
4.1.2 Interrupt
4.1.3 Register Structure
4.2 Register Addresses
4.3 Register Definitions
4.3.1 Register 0–MAC Address 1
4.3.2 Register 1–MAC Address 2
4.3.3 Register 2–MAC Address 3
4.3.4 Register 3–MAC Address Filter 1
4.3.5 Register 4–MAC Address Filter 2
4.3.6 Register 5–MAC Address Filter 3
4.3.7 Register 6–MAC Address Filter 4
4.3.8 Register 7–Configuration 1
4.3.9 Register 8–Configuration 2
4.3.10 Register 9–Configuration 3
4.3.11 Register 10–Configuration 4
4.3.12 Register 11–Status 1
4.3.13 Register 14–Status Mask 1
4.3.14 Register 17–Transmit FIFO Threshold
4.3.15 Register 18–Receive FIFO Threshold
4.3.16 Register 19–Flow Control 1
4.3.17 Register 20–Flow Control 2
4.3.18 Register 21–AutoNegotiation Base Page
Transmit
4.3.19 Register 22–AutoNegotiation Base Page
Receive
4.3.20 Register 23–AutoNegotiation Next Page
Transmit
4.3.21 Register 24–AutoNegotiation Next Page
Receive
4.3.22 Register 32–Device ID
4.3.23 Register 112–115–Counter Half Full 1−4
4.3.24 Registers 120–123–Counter Half Full Mask 1−4
4.3.25 Registers 128−233–Counter 1−53
4-1
4-2
4-3
4-4
4-4
4-11
4-11
4-12
4-12
4-12
4-13
4-14
4-14
4-15
4-17
4-19
4-22
4-23
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-33
4-34
4-35
4-36
4-36
4-37
Contents
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