8101 Datasheet, PDF (90/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

rising edge of REGCLK, the address of the register that is accessed is
clocked in on REGA[7:0]. On that same rising edge of REGCLK, either
REGRDn or REGWRn must also be asserted. These signals determine
whether the register access is a read or write cycle. During a write cycle,
the data to be written to a specific register is clocked in on the rising
edge of the same clock that clocked in the other inputs. During a read
cycle, the data is output on REGD[15:0] some delay after the rising edge
of REGCLK that clocked in the input information. REGCSn can remain
LOW for multiple REGCLK cycles so that many registers can be read or
written during one REGCSn assertion.
During read cycles, the delay from REGCLK to data valid on the
REGD[15:0] pins is a function of which register is being accessed. Data
read from any register, exclusive of the Counter 1−53 registers, appears
on the REGD[15:0] pins in one REGCLK cycle. Data read from the
Counter 1−53 registers takes at most six REGCLK cycles to be available
on REGD[15:0] for the first 16 bits of the counter result, and at most
three REGCLK cycles for the second 16 bits of the counter result. Refer
to Chapter 6, Specifications for details of the interface timing
characteristics.
4.1.1 Bit Types
The register interface is bidirectional, and there are many types of bits in
the registers. The bit type definitions are summarized in Table 4.1. Write
bits (W) are inputs during a write cycle and are 0 during read cycles.
Read bits (R) are outputs during a read cycle and ignored and high-
impedance during a write cycle. Read/Write bits (R/W) are actually write
bits that can be read during a read cycle. R/WSC bits are R/W bits that
are self clearing after a set period of time or after a specific event has
completed. R/LL bits are read bits that latch themselves when they go to
0 and they stay latched until read. After they are read, they are set to 1.
R/LH bits are the same as R/LL bits except that they latch to 1. R/LT are
read bits that latch themselves whenever they make a transition or
change value and they stay latched until they are read. After R/LT bits
are read, they are updated to their current value. R/LLI, R/LHI, and R/LTI
bits function the same as R/LL, R/LH and R/LT bits, respectively, except
they also assert interrupt if programmed to do so (not masked).
4-2
Registers
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