8101 Datasheet, PDF (31/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

Figure 2.5 RXSOF/RXEOF Position
RX FIFO Data
First Data Word
RXSOF/RXEOF Position
Bits 7.2 – 7.0 (STSWRD [1:0], PEOF)
00X
010
011
100
101
11X
SOF
SOF
SOF
SOF
SOF
Packet
Data
Last Data Word
Status Word
Discard Status Word
EOF
[1]
[1]
EOF
[1]
EOF
R
e
s
e
r
v
e
d
EOF
EOF
[1] SOF, EOF SOF, EOF
Note:
[1] Status words do not exist with this bit combination
The RXWM1 and RXWM2 signals indicate when the receive FIFO has
exceeded the programmable watermark thresholds. The watermarks are
asserted or deasserted on the rising edge of SCLK, depending on the
fullness of the receive FIFO. Refer to Section 2.10, “Receive FIFO,” for
more details on these watermarks.
RXDC is asserted every time a received packet being output over the
system interface is halted and the packet discarded due to some error.
This signal is latched HIGH and can be cleared by either asserting the
clearing signal, CLR_RXDC, or cleared automatically if the controller is
placed in the AutoClear mode. See Section 2.13, “Packet Discard,”
section for more details on discards and RXDC.
The RXABORT input, when asserted, discards the current packet being
output on the system interface. When RXABORT is asserted, a packet
is discarded and the remaining contents of that packet in the receive
FIFO are flushed. The process of flushing a receive packet from the
receive FIFO with the RXABORT pin requires extra SCLK cycles equal
to (packet length in bytes)/8 + 6. Refer to Section 2.13, “Packet Discard,”
for more information about discarded packets. Clearing the discard
RXABORT enable bit in “Register 8–Configuration 2‚" Section 4.3.9,
programs the controller to ignore the RXABORT signal. Setting the
System Interface
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