8101 Datasheet, PDF (50/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

The 10-bit PHY interface consists of 26 signals as follows:
• Ten bit transmit data output bits (TX[9:0])
• Transmit clock output (TBC)
• Ten bit receive data input bits (RX[9:0])
• Two receive clock inputs (RBC0 and RBC1)
• Comma detect enable output (EN_CDET)
• Loopback output (EWRAP)
• Receiver lock output (LCK_REFn)
2.12.1 Data Format and Bit Order
The format and bit order of the data word on TX[9:0] and RX[9:0] and its
relationship to the MAC frame and the system interface data words is
shown in Figure 2.3. Note that Figure 2.3 assumes the controller is in
Little Endian format (default). If the controller is in Big Endian format, the
byte order of the system interface data word is reversed. See
Section 2.6, “System Interface” for more details.
2.12.2 Transmit
On the transmit side, the TBC output clock is generated from the TCLK
input clock and runs continuously at 125 MHz. Data on TX[9:0] is clocked
out of the controller on the rising edge of the TBC clock output.
2.12.3 Receive
On the receive side, RX[9:0] data is clocked in on rising edges of the
RBC[1:0] input clocks. RBC1 and RBC0 are required to be at a
frequency of 62.5 MHz and be 180° out of phase. The data on RX[9:0]
is clocked in at an effective 125 MHz using alternate rising edges of the
RBC[1:0] clocks to latch in the data on RX[9:0]. The incoming data on
RX[9:0] is also required to be word aligned to the RBC1 clock, (the words
that contain comma codes must be clocked in with the RBC1 clock, as
specified in IEEE 802.3z).
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Functional Description
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