8101 Datasheet, PDF (27/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

shown in Figure 2.3. Note that the controller can be programmed to
append an additional 32-bit status word to the end of the receive packet.
Refer to Section 2.14, “Receive Status Word,” for more details on this
status word.
To program the byte ordering of the TXD and RXD data bits, set the
endian bit in “Register 10–Configuration 4‚" Section 4.3.11. The byte
order shown in Figure 2.4 is with the little endian format mode (default).
If the controller is placed in big endian format, the byte order shown in
Figure 2.4 is reversed, DA[0:7] occurs on pins RXD[24:31], DA[24:31]
occurs on pins RXD[0:7]and so on. The endian bit affects all bytes in the
frame including the receive status word (if appended). The difference
between little endian and big endian format is illustrated in Figure 2.4.
Figure 2.4 Little Endian vs. Big Endian Format
Little
Endian
(Default)
TXD[8] . . . TXD[15]
RXD[8] . . . RXD[15]
TXD[24] . . . TXD[31]
RXD[2]4 . . . RXD[31]
TXD[8] . . . TXD[15]
RXD[8] . . . RXD[15]
TXD[0] . . . TXD[7]
RXD[0] . . . RXD[7]
TXD[16] . . . TXD[23]
RXD[16] . . . RXD[23]
TXD[0] . . . TXD[7]
RXD[0] . . . RXD[7]
TXD[16] . . .
RXD[16] . . .
Preamble
DA0 . .. . . DA7 DA8 . . . . DA15 DA16 . . . DA23 DA24 . . . DA31 DA32 . . . DA39 DA40 . . . DA47 Source Address
Big
Endian
TXD[24] . . . TXD[31]
RXD[24] . . . RXD[31]
TXD[8] . . . TXD[15]
RXD[8] . . . RXD[15]
TXD[24] . . . TXD[31]
RXD[24] . . . RXD[31]
TXD[15] . . .
RXD[15]] . . .
TXD[16]. . . TXD[23]
RXD[16] . . . RXD[23]
TXD[0] . . . TXD[7]
RXD[0] . . . RXD[7]
TXD[16] . . . TXD[23]
RXD[16] . . . RXD[23]
2.6.2 Transmit Timing
The transmit portion of the system interface consists of 45 signals:
32 transmit data input bits (TXD[31:0]), one transmit enable (TXENn),
four transmit byte enable inputs (TXBE[3:0]), two transmit start of frame
and end of frame inputs (TXSOF and TXEOF), two transmit FIFO
watermark outputs (TXWM1n and TXWM2n), one transmit discard output
(TXDC), one transmit discard clear input (CLR_TXDC), one transmit
CRC enable input (TXCRCn), and one flow control enable input
(FCNTRL). All receive and transmit data is clocked in and out on the
rising edge of the system clock, SCLK. SCLK must operate between
33–66 MHz.
The SCLK input needs to be continuously input to the controller at
33–66 MHz. When TXENn is deasserted, the transmit interface is not
selected and subsequently, the controller accepts no input data from the
System Interface
2-9
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