8101 Datasheet, PDF (21/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

Figure 2.1 8101/8104 Block Diagram
RESETn
SCLK
MAC
8B10B PCS
TXENn
TXD[31:0]
TXBE[3:0]
TXSOF
TXEOF
TXWM1n
TXWM2n
TXDC
CLR_TXDC
TXCRCn
FCNTRL
RXENn
RXD[31:0]
RXBE[3:0]
RXSOF
RXEOF
RXWM1
RXWM2
RXDC
CLR_RXDC
RXABORT
RXOEn
System
Interface
Transmit
FIFO
CRC
Generator
MAC Control
Frame Gen.
Packet
Generator
8B10B
Encoder
Transmit
Receive
FIFO
Transmit
Receive
MAC Control
Frame Check
Address
Filter
CRC
Check
Transmit
Receive
Link
Configuration
Receive
Sync.
REGCLK
REGCSn
REGD[15:0]
REGAD[7:0]
REGRDn
REGWRn
REGINT
Register
Interface
&
Registers
Packet
Decompose
Management
Counters
8B10B
Decoder
Receive
TCLK
TX[9:0]
TBC
10-Bit
PHY
Interface
EWRAP
LCK_REFn
EN_CDET
RX[0:9]
RBC[1:0]
LINKn
SD