8101 Datasheet, PDF (20/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

2.1 Overview
The 8101/8104 is a complete Media Access Controller (MAC) sublayer
with integrated coding logic for fiber and short haul copper media (8B10B
PCS sublayer) for 1000 Mbits/s Gigabit Ethernet systems. The controller
has seven main sections:
• System interface
• FIFOs
• MAC
• 8B10B PCS
• 10-bit PHY interface
• Register interface.
• Management counters
A block diagram is shown in Figure 2.1.
The controller has a transmit data path and a receive data path. The
transmit data path goes in the system interface and out the 10-bit PHY
interface, as shown in the top half of Figure 2.1. The receive data path
goes in the 10-bit PHY interface and out the system interface, as shown
in the bottom half of Figure 2.1.
2.2 Transmit Data Path
Data is input to the system from an external bus. The data is then sent
to the transmit FIFO. The transmit FIFO provides temporary storage of
the data until it is sent to the MAC transmit section. The transmit MAC
formats the data into an Ethernet packet according to IEEE 802.3
specification as shown in Figure 2.2. The transmit MAC also generates
MAC control frames and includes logic for AutoNegotiation. The Ethernet
frame packet is then sent to the 8B10B PCS.
The 8B10B PCS encodes the data and adds appropriate framing
delimiters to create 10-bit symbols as specified in IEEE 802.3 and shown
in Figure 2.3. The 10-bit symbols are then sent to the 10-bit PHY
interface for transmission to an external PHY device.
2-2
Functional Description
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