8101 Datasheet, PDF (54/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

The controller can be programmed to send status words for discarded
packets to the receive FIFO. See Section 2.14, “Receive Status Word”
for more details on status word configuration.
Note:
Receive FIFO underflow is not listed as a discard condition
in Table 2.10, (packets are not discarded when corrupted
by receive FIFO underflow). However, receive FIFO
underflow does cause the assertion of RXDC.
2.13.3 Discard Output Indication
When a discard condition is detected on a packet being received or
transmitted over the system interface, the TXDC and RXDC output pins
are asserted to indicate that the discard error was detected. TXDC and
RXDC are normally latched HIGH when a discard takes place. Asserting
CLR_TXDC and CLR_RXDC clearing pins, clears the TXDC and RXDC
outputs.
2.13.4 AutoClear Mode
Programming the controller to be in the AutoClear mode automatically
self clears the TXDC and RXDC pins. To program the controller for the
AutoClear mode, set the AUTOCLR bit in “Register 9–Configuration 3‚"
Section 4.3.10. When the controller is in the AutoClear mode, TXDC and
RXDC are automatically cleared three SCLK cycles after the next end of
packet occurs.
2.13.5 AutoAbort Mode
When the AutoAbort mode is enabled the controller can also
automatically abort the current packet on the system interface in the
receive FIFO when a discard condition is detected and RXDC is
asserted. Set the AUTORXAB bit in “Register 9–Configuration 3‚"
Section 4.3.10, to enable the AutoAbort mode.
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Functional Description
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