8101 Datasheet, PDF (83/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

RXWM1
RXWM2
SCLK
TXBE[3:0]
TXCRCn
TXD[31:0]
Receive FIFO Watermark 1
Output
When RXWM1 is LOW, the receive FIFO data is less
than or equal to the receive FIFO watermark 1 threshold.
When HIGH, the receive FIFO data is greater than the
watermark. RXWM1 is clocked out on the rising edge of
the system clock, SCLK. Data is valid on RXD[31:0] when
either RXWM1 or RXWM2 is asserted, independent of
RXENn.
Receive FIFO Watermark 2
Output
When RXWM2 is LOW, the receive FIFO data is less
than or equal to the receive FIFO watermark 2 threshold
and no EOF in FIFO. When HIGH, the receive FIFO data
is greater than the watermark. RXWM2 is clocked out on
the rising edge of the system clock, SCLK. Data is valid
on RXD[31:0] when either RXWM1 or RXWM2 is
asserted, independent of RXENn.
System Interface Clock
Input
This input clocks data in and out of the transmit and
receive FIFOs on TXD[31:0] and RXD[31:0], respectively.
All system interface inputs and outputs are also clocked
in and out on the rising edge of SCLK, with the exception
of RXOEn. SCLK clock frequency must be between
33–66 MHz.
Transmit Byte Enable
Input
These inputs determine which bytes of the current 32-bit
word on TXD[31:0] contain valid data. TXBE[3:0] is
clocked into the device on the rising edge of the system
interface clock, SCLK.
Transmit CRC Enable
Input
When TXCRC is LOW, CRC is calculated and appended
to the current packet being input on the system interface.
When TXCRC is HIGH, CRC is not calculated. TXCRCn
is clocked in on the rising edge of the system clock,
SCLK, and must be asserted on the same SCLK clock
cycle as TXSOF.
Transmit Data
Input
This input bus contains the 32-bit data word that is
clocked into the transmit FIFO on the rising edge of the
system interface clock, SCLK.
System Interface Signals
3-5
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