8101 Datasheet, PDF (51/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

The comma detect output, EN_CDET, is asserted when the receiver in
the 8B10B PCS section has lost word synchronization.Setting the CDET
bit in “Register 9–Configuration 3‚" Section 4.3.10, also asserts
EN_CDET. The EN_CDET output can be used to enable the bit
synchronization process in an external physical layer device.
The controller does not have a pin designated for the standardized
comma detect input, COM_DET, because the receive 8B10B PCS
section has all the necessary logic to acquire word synchronization from
the contents of the receive data stream alone.
2.12.4 Lock To Reference
Setting the LCKREFn bit in “Register 9–Configuration 3‚" Section 4.3.10,
exclusively controls the LCK_REFn output. This output is typically used
to enable the PLL locking process in an external physical layer device.
2.12.5 PHY Loopback
Setting the EWRAP bit in “Register 9–Configuration 3‚" Section 4.3.10,
exclusively controls the EWRAP output. This output is typically used to
enable a loopback function in an external physical layer device.
When the EWRAP pin is asserted, the signal detect input pin, SD, from
an external physical layer device may be in an unknown state. To
counteract this, the SD_EN bit in Register 9 “Configuration 3” should also
be cleared when the EWRAP assert bit is set.
2.12.6 Signal Detect
There is an additional signal detect input pin, SD, which indicates to the
controller that the receive data detected on RXD[9:0] contains valid data.
If SD is asserted, the input data is assumed valid and the receive 8B10B
PCS section is unaffected. If SD is deasserted, the data is assumed to
be invalid and the receive 8B10B PCS section is forced into the loss of
sync state. Although SD is not part of the IEEE-defined 10-bit PHY
interface, it is typically sourced from an external physical layer device.
The controller powers up with the SD pin disabled (SD has no affect on
the receive word synchronization state machine). To enable the SD pin,
the SD_EN bit must be set in “Register 9–Configuration 3‚"
Section 4.3.10.
10-Bit PHY Interface
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