8101 Datasheet, PDF (105/172 Pages) LSI Computer Systems – Gigabit Ethernet Controller

RXCRC
Receive CRC Enable
3, R/W
RXCRC
Description
1
CRC is stored in RX FIFO with rest of packet
0
CRC stripped off
STSWRD[1:0] Receive Status Word Append Select
[2:1], R/W
STSWRD[1:0] Description
11
Reserved
10
Receive status word for nondiscarded packets
and discarded packets
01
Receive status word for nondiscarded packets
00
No receive status word
PEOF
Receive EOF Position Select
0, R/W
PEOF
1
0
Description
Receive EOF at end of packet data
Receive EOF at end of receive status word
4.3.9 Register 8–Configuration 2
15
REJUCST
14
REJMCST
13
REJBCST
12
REJALL
11
ACPTALL
10
DIS_OVF
9
8
DIS_CRC DIS_USIZE
7
6
5
4
0
DIS_OSIZE DIS_CWRD DIS_RXAB
RES = 0
Note: REJUCST 15-bit occurs on the REGD15 pin
REJUCST
Receive Unicast Packets Reject
15, R/W
REJUCST Description
1
Receiver rejects all unicast packets
0
Accept unicast packet if DA value in registers [0:2]
Register Definitions
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