MC68HC05PV8 Datasheet, PDF (98/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
PALIE – PA0–3 Interrupt Enable Lower Nibble
This bit disables/enables the PA0–3 pins as interrupt group.
1 = PA0–3 interrupt enabled
0 = PA0–3 interrupt disabled
VRLEN – Enable A/D Low Reference Channel
This bit connects the PA0 pin with the A/D low reference channel.
1 = A/D low reference channel connected to external VREFL.
0 = A/D low reference channel connected to internal ground.
7.4.5 Port A Interrupt Status Register
$0024 Bit 7
6
5
4
3
2
1
Read:
Write:
PAIF7
PAIF6
PAIF5
PAIF4
PAIF3
PAIF2
PAIF1
Reset: 0
0
0
0
0
0
0
Figure 7-3 Port A Interrupt Status Register (PAISR)
Bit 0
PAIF0
0
PAIF0–7 – Port A Interrupt Flags
These flags indicate which of the port A interrupt requests is pending.
The 8 interrupt flags can be reset individually if a 1 is written to the bit
position.
1 = Flag set when corresponding transition is sensed (if interrupt
enabled). Writing a 1 clears the flag
0 = No interrupt. Writing a 0 has no effect
7.4.6 Operational Amplifier
Pins PA4–6 are connected to an operational amplifier. The operational
amplifier is intended for amplifying small signals over VSS to increase
the resolution of the A/D converter. The output stage of this operational
amplifier is asymmetrical and thus optimized for driving loads to VSS
while keeping the quiescent current low. The output of the operational
amplifier is connected to channel 4 of the A/D converter. The amplifier is
enabled by the I/O configuration register Bit6. As long as IOCFG Bit6 is
0, the presence of the operational amplifier is without any effect. If the
opamp is enabled, first ensure that the PA4 is switched to input mode.
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
Input/Output Ports
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