MC68HC05PV8 Datasheet, PDF (143/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
Analog to Digital Converter
A/D During STOP Mode
10.8 A/D During STOP Mode
In STOP mode the comparator and charge pump are turned off and the
A/D ceases to function. Any pending conversion is aborted. When the
clocks begin oscillation upon leaving the STOP mode, a finite amount of
time passes before the A/D circuits stabilize enough to provide
conversions to the specified accuracy. Normally the delays built into the
device when coming out of STOP mode are sufficient for this purpose
therefore no explicit delays need to be built into the software.
Although the comparator and charge pump are disabled in STOP mode
the A/D data and status/control registers are not modified. Disabling the
A/D prior to entering STOP mode will not affect the STOP mode current
consumption.
10.9 Analog Input
The external analog voltage value to be converted by the A/D converter
is sampled on an internal capacitor through a resistive path provided by
input-selection switches and a sampling aperture time switch. Sampling
time is limited to 12 bus clock cycles. After sampling, the analog value is
stored on a capacitor and held until the end of conversion. During this
hold time, the analog input is disconnected from the internal A/D system
and the external voltage source sees a high impedance input.
The equivalent analog input during sampling is a RC low-pass filter with
resistance around 50 kΩ and a capacitance of around 8pF. (It should be
noted that these are typical values measured at room temperature).
MC68HC(8)05PV8/A — Rev. 1.9
Analog to Digital Converter
For More Information On This Product,
Go to: www.freescale.com
Technical Data