MC68HC05PV8 Datasheet, PDF (121/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
Core Timer
Registers
8.3.2 Computer Operating Properly (COP) Watchdog Reset
The COP watchdog timer function is implemented on this device by
using the output of the RTI circuit and further dividing it by eight. The
minimum COP reset rates are listed in Table 8-2. If the COP circuit times
out, an internal reset is generated and the normal reset vector is fetched.
A COP time-out is prevented by clearing bit 0 of address $3FF0. When
the COP is cleared, only the final divide by eight stage (output of the RTI)
is cleared.
RT1:RT0
00
01
10
11
Table 8-2 Minimum COP Reset Times
Minimum COP Reset Bus Frequency at f_OP specified:
500 kHz
1.000 MHz 2.000 MHz 2.4576 MHz
RATIO
229.376ms
458.752ms
917.504ms
1835.000ms
114.689ms
229.376ms
458.752ms
917.504ms
57.344ms
114.689ms
229.376ms
458.752ms
46.666ms
93.333ms
186.666ms
373.333ms
7*2¹⁴/f_op
7*2¹⁵/f_op
7*2¹⁶/f_op
7*2¹⁷/f_op
8.3.3 Core Timer Counter Register (CTCR)
The timer counter register is a read-only register which contains the
current value of the 8-bit ripple counter at the beginning of the timer
chain. This counter is clocked at f_op divided by 4 and can be used for
various functions including a software input capture. Extended time
periods can be attained using the TOF function to increment a temporary
RAM storage location thereby simulating a 16-bit (or more) counter.
$0009 Bit 7
6
5
4
3
2
1
Bit 0
Read: bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 8-3 Core Timer Counter Register (CTCR)
MC68HC(8)05PV8/A — Rev. 1.9
Core Timer
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Technical Data