MC68HC05PV8 Datasheet, PDF (130/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
The free-running counter contents are transferred to the input capture
register on each proper signal transition regardless of whether the input
capture flag (IC1F) is set or clear. The input capture register always
contains the free-running counter value that corresponds to the most
recent input capture.
After a read of the input capture register most significant byte ($10), the
counter transfer is inhibited until the least significant byte ($11) is also
read. This characteristic causes the time used in the input capture
software routine, and its interaction with the main program, to determine
the minimum pulse period.
A read of the input capture register LSB ($11) does not inhibit the
free-running counter transfer since they occur on opposite edges of the
internal bus clock.
9.3.3.2 Input Capture Register 2
Two 8-bit registers, which make up the 16-bit input capture register 2,
are read-only and are used to latch the value of the free-running counter
after the corresponding input capture edge detector senses a defined
transition on the TCAP2 pin. The level transition which triggers the
counter transfer is defined by the corresponding input edge bit (IEDG2).
Reset does not affect the contents of the input capture register except
when exiting stop mode.
IEDG2 – Capture on Negative/Positive Edge
1 = Capture on positive edge
0 = Capture on negative edge
An interrupt can also accompany a capture provided the corresponding
interrupt enable bit, ICI2E, is set.
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter,
which is four internal bus clock cycles.
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
16-Bit Programmable Timer
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