MC68HC05PV8 Datasheet, PDF (129/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
16-Bit Programmable Timer
Registers
The processor can write to either byte of the output compare register 2
without affecting the other byte. The output level (OLVL2) bit is clocked
to the output level register regardless of whether the output compare flag
(OC2F) is set or clear.
Because the output compare flag OC2F and the output compare register
2 are undetermined at power-on, and are not affected by external reset,
care must be exercised when initializing the output compare function. A
procedure as recommended for compare register 1 should be followed.
9.3.3 Input Capture Registers
There are two identical input capture registers: Input capture register 1
and input capture register 2. The two following sections describe these
two registers.
9.3.3.1 Input Capture Register 1
Two 8-bit registers, which make up the 16-bit input capture register 1,
are read-only and are used to latch the value of the free-running counter
after the corresponding input capture edge detector senses a defined
transition on the TCAP1 pin. The level transition which triggers the
counter transfer is defined by the corresponding input edge bit (IEDG1).
Reset does not affect the contents of the input capture register except
when exiting stop mode.
IEDG1 – Capture on Negative/Positive Edge
1 = Capture on positive edge
0 = Capture on negative edge
An interrupt can also accompany a capture provided the corresponding
interrupt enable bit, ICI1E, is set.
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter
which is four internal bus clock cycles.
MC68HC(8)05PV8/A — Rev. 1.9
16-Bit Programmable Timer
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Technical Data