MC68HC05PV8 Datasheet, PDF (148/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
Loadable Counter
OSC1
Clock Generator ^fPWM
Comparator
Buffer
PWM
Pin Logic
PWM
PWM Control Register
Figure 11-1 PWM Block Diagram
11.3 Functional Description
The PWM is capable of generating signals from 0% to 100% duty cycle.
A $00 in the PWM data register yields an OFF output (0%), but an $FF
yields a duty of 255/256 (assuming the PWM period register is set to
$FF). To achieve the 100% duty (ON output), the polarity control bit is
set while the data register contains $00. When not in use the PWM
system can be shut off to save power by clearing the PWMON bit in the
PWM control register. The PWM starts conversion immediately after
setting PWMON. The PWM output can have an active high or an active
low pulse under software control.
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
Pulse Width Modulator
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