MC68HC05PV8 Datasheet, PDF (94/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
7.2 Introduction
In single chip mode there are 20 lines arranged as one 8-bit I/O port (port
A), one 5-bit I/O port (port B), and one 7-bit high-voltage I/O port (port
C). The I/O ports are programmable as either inputs or outputs under
software control of the data direction registers (see 7.3 General
Input/Output Programming).
Port A is shared with A/D channels. Ports B and C are shared with timer
and PWM channels. Port C comprises 5 lines with contact sensors and
2 lines with low side drivers.
7.3 General Input/Output Programming
Bidirectional port lines may be programmed as an input or an output
under software control. The direction of the pins is determined by the
state of the corresponding bit in the port data direction register (DDR).
Each port has an associated DDR. Any I/O port pin is configured as an
output if its corresponding DDR bit is set to a logic one. A pin is
configured as an input if its corresponding DDR bit is cleared to a logical
zero (see Table 7-1 and Figure 7-1).
At power-on or reset, all DDRs are cleared, thus configuring all port pins
as inputs. Reset does not affect the state of the data bits, thus after
power-on reset their state is unknown. The data direction registers are
capable of being written to or read by the processor. During the
programmed output state, a read of the data register actually reads the
value of the output data latch and not the I/O pin.
Table 7-1 I/O Pin Functions
R/W^{(1) DDR}
I/O Pin Function
0
0 The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is in output mode. The output data latch is read.
1. R/W is an internal signal
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
Input/Output Ports
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