MC68HC05PV8 Datasheet, PDF (67/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
Interrupts
CPU Interrupt Processing
When an interrupt is to be processed, the CPU fetches the address of
the appropriate interrupt software service routine from the vector table at
locations $3FF0 through $3FFF as defined in Table 4-1.
Table 4-1 Reset/Interrupt Vector Addresses
Function
Reset
Software Interrupt (SWI)
External Interrupt
Core Timer Interrupts
16-Bit Timer Interrupts
Source
Power-On Logic
RESET Pin
COP Watchdog
Low Voltage
High Voltage
High Temperature
Clock Monitor
Illegal STOP Inst.
Illegal Address
Local
Mask
None
Mask
Options
None
User Code
None
IRQ Pin
RTIF
TOF
ICF Bits
OCF Bits
TOF Bit
INTE Bit
RTIE Bit
TOFE Bit
ICIE Bits
OCIE Bits
TOIE Bit
Global
Mask
None
None
I-Bit
I-Bit
I-Bit
Priority
(1 = Highest)
Vector
Address
1
$3FFE–$3FFF
Same Priority
As
Instruction
2
$3FFC–$3FFD
$3FFA–$3FFB
3
$3FF8–$3FF9
4
$3FF6–$3FF7
MC68HC(8)05PV8/A — Rev. 1.9
Interrupts
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Technical Data