MC68HC05PV8 Datasheet, PDF (119/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
8.3 Registers
Core Timer
Registers
8.3.1 Core Timer Status & Control Register (CTSCR)
The CTSCR contains the timer interrupt flag, the timer interrupt enable
bits, and the real time interrupt rate select bits. Figure 8-2 shows the
value of each bit in the CTSCR when coming out of reset.
$0008 Bit 7
6
5
4
3
2
1
Bit 0
Read: TOF
RTIF
0
0
TOFE RTIE
RT1
RT0
Write:
RTOF RRTIF
Reset: 0
0
0
0
0
0
1
1
Figure 8-2 Core Timer Status and Control Register (CTSCR)
TOF – Timer Over Flow
TOF is a read-only status bit and is set when the 8-bit ripple counter
rolls over from $FF to $00. A CPU interrupt request will be generated
if TOFE is set. Reset clears TOF.
RTIF – Real Time Interrupt Flag
The real time interrupt circuit consists of a three stage divider and a 1
of 4 selector. The clock frequency that drives the RTI circuit is f_op/2¹³
(or f_op/8192) with three additional divider stages giving a maximum
interrupt period of about 250ms at a crystal frequency of 1 MHz. RTIF
is a read-only status bit and is set when the output of the chosen (1 of
4 selection) stage goes active. A CPU interrupt request will be
generated if RTIE is set. Reset clears RTIF.
TOFE – Timer Over Flow Enable
When this bit is set, a CPU interrupt request is generated when the
TOF bit is set. Reset clears this bit.
RTIE – Real Time Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the
RTIF bit is set. Reset clears this bit.
MC68HC(8)05PV8/A — Rev. 1.9
Core Timer
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Technical Data