MC68HC05PV8 Datasheet, PDF (142/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
CH3
1
1
1
1
1
Table 10-1 A/D Channel Assignments
CH2
0
0
0
0
1
CH1
0
0
1
1
X
CH0
0
1
0
1
X
Channel
8
9
10
11
12-15
Signal
V_REFH
(V_REFH+V_REFL)/2
V_REFL
V_REFL
V_REFL
NOTE: Channel 0 and 7–15 convert internal signals which cannot be accessed
externally.
10.6.2 A/D Data Register
One 8-bit result register is provided. This register is updated each time
COCO is set.
$000E Bit 7
6
5
4
3
2
1
Bit 0
Read: bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Write:
Reset: U
U
U
U
U
U
U
U
Figure 10-3 A/D Data Register (ADDR)
10.7 A/D During WAIT Mode
The A/D converter continues normal operation during WAIT mode. To
decrease power consumption during WAIT it is recommended that both
the ADON and ADRC bits in the A/D status and control registers be
cleared if the A/D converter is not being used. If the A/D converter is in
use and the system clock rate is above 1.0 MHz it is recommended that
the ADRC bit be cleared.
As the A/D converter continues to function normally in WAIT mode the
COCO bit is not cleared.
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
Analog to Digital Converter
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