MC68HC05PV8 Datasheet, PDF (79/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
Resets
External Reset (RESET)
HTR – High Temperature Reset Bit
1 = Last reset caused by high temperature detect circuitry
0 = No high temperature reset since HTR was cleared by software
or POR
HVR – High Voltage Reset Bit
1 = Last reset caused by high voltage detect circuitry
0 = No high voltage reset since HVR is cleared by software or POR
LVR – Low Voltage Reset Bit
1 = Last reset caused by low voltage detect circuitry
0 = No low voltage reset since LVR was cleared by software or
POR
Note: If the cause of an environmental reset only lasts for a short time and if there is an external
capacitor on the RESET pin, the corresponding bit in the reset status register may be set without
occurrence of a reset.
5.4 External Reset (RESET)
The RESET pin is the only external source of a reset. This pin is
connected to a Schmitt trigger input gate to provide an upper and lower
threshold voltage separated by a minimum amount of hysteresis. This
external reset occurs whenever the RESET pin is pulled below the lower
threshold and remains in reset until the RESET pin rises above the upper
threshold. This active low input generates the RST signal and resets the
CPU and peripherals.
Activation of the RST signal is generally referred to as reset of the
device, unless otherwise specified.
The RESET pin can also act as an open drain output. It is pulled to a low
state by an internal pull-down that is activated by any reset source. This
RESET pull-down device is asserted until the internal reset source is
deasserted and the reset is internally recognized.
MC68HC(8)05PV8/A — Rev. 1.9
Resets
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Technical Data