MC68HC05PV8 Datasheet, PDF (100/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
7.5 Port B
Port B is a 5-bit bidirectional port, shared with timer and PWM channels
(TCAP, TCMP, PWM). An XOR function is provided for one timer
capture channel.
The port B data register is at $0001 and the data direction register (DDR)
is at $0005. Reset does not affect the data registers, but clears the data
direction registers, thereby returning the ports to inputs. Writing a one to
a DDR bit sets the corresponding port bit to output mode.
7.5.1 Port B Timer Channels and XOR Function
The port pins PB0–PB3 are shared with the 16-bit timer channels
(TCAP1–2, TCMP1–2). The timer capture channel TCAP1 can be driven
by the XOR of two channels if TXOR bit in the I/O Configuration Register
is set (see Figure 7-6).TCAP1 status can be read by the CPU by polling
bit 5 of the Port B Data Register.
FROM PC0 OR C4
PB0
PC2
PB2
0
1
PB0IC
0
1
PB2IC
0
1
TCAP1
TXOR
Capture
Channel 1
Capture
Channel 2
Technical Data
Figure 7-6 Mapping Ports to Timer Capture Channels
MC68HC(8)05PV8/A — Rev. 1.9
Input/Output Ports
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