MC68HC05PV8 Datasheet, PDF (122/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
The power-on cycle clears the entire counter chain and begins clocking
the counter. After 4064 cycles, the power-on reset circuit is released
which again clears the counter chain and allows the device to come out
of reset. At this point, if RESET is not asserted, the timer will start
counting up from zero and normal device operation will begin. When
RESET is asserted anytime during operation (other than POR), the
counter chain will be cleared.
8.4 Core Timer During WAIT
The CPU clock halts during the WAIT mode but the core timer remains
active. If the CTIMER interrupts are enabled, then a CTIMER interrupt
will cause the processor to exit the WAIT mode.
8.5 Core Timer During STOP
The timer and the interrupt mask and enable flags are cleared when
going into STOP mode. When STOP is exited by an external interrupt or
an external reset the internal oscillator will restart, followed by an internal
processor stabilization delay (t_PORL). The timer is then cleared and the
operation resumes.
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
Core Timer
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