MC68HC05PV8 Datasheet, PDF (156/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
Any loss of V_DD sufficient to trigger an LVR causes the device to be
reset. The device remains in the reset state for the duration of the LVR
condition or until the internal V_DD drops below the functional level of the
device, at which point reset no longer has meaning. If the drop in V_DD
that triggers an LVR is transient, then an internal RST is asserted for a
minimum 4064 cycles of the CPU bus clock, PH2 (the POR delay).
On the MC68HC05PV8A, the low voltage reset is generated by a second
low voltage reset generator with a lower threshold as long as the ULPM
bit is set. For this reason, it is mendatory to have the ULPM bit cleared
as long as the mcu is in normal operation.
12.5 Trimming the Voltage Regulator
The output of the voltage regulator can be trimmed to reach a higher
accuracy. This is performed by setting the VT2, VT1 and VT0 bits in the
MFTEST register
$002F Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
HVTOFF
Write:
–
0
VSCAL LSOFF VT2
VT1
VT0
–
Reset: 0
0
0
0
0
0
0
0
Figure 12-1 MFTEST Register (MFTEST)
Table 12-1 illustrates the effect of the trimming bits to V_DD in increase or
decrease of the output voltage by trimming steps (typically 40mV).
Table 12-1 Trimming Effect
VT2 VT1 VT0 Effect
0
0
0
±0
0
0
1
–1
0
1
0
–2
0
1
1
–3
1
0
0
+4
1
0
1
+3
1
1
0
+2
1
1
1
+1
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
Voltage Regulator
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