MC68HC05PV8 Datasheet, PDF (131/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
16-Bit Programmable Timer
Registers
The free-running counter contents are transferred to the input capture
register on each proper signal transition regardless of whether the input
capture flag (IC2F) is set or clear. The input capture register always
contains the free-running counter value that corresponds to the most
recent input capture.
After a read of the input capture register most significant byte ($14), the
counter transfer is inhibited until the least significant byte ($15) is also
read. This characteristic causes the time used in the input capture
software routine, and its interaction with the main program, to determine
the minimum pulse period.
A read of the input capture register LSB ($15) does not inhibit the
free-running counter transfer since they occur on opposite edges of the
internal bus clock.
9.3.4 Timer Control Register 1
$001C
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
ICI1E ICI2E OCI1E TOIE OCI2E
0
0
0
0
0
U
U
Figure 9-2 Timer Control Register 1 (TCR1)
Bit 0
TOFF
0
ICI1E – Input Capture 1 Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
ICI2E – Input Capture 2 Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
OCI1E – Output Compare 1 Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
TOIE – Timer Overflow Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
MC68HC(8)05PV8/A — Rev. 1.9
16-Bit Programmable Timer
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Technical Data