MC68HC05PV8 Datasheet, PDF (61/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
CPU and Instruction Set
Instruction Set Summary
Source
Form
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NOP
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
Table 3-6 Instruction Set Summary (Continued)
Operation
Jump to Subroutine
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
Logical Shift Right
Description
Effect on
CCR
H I NZC
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
A ← (M)
X ← (M)
C
b7
0
b0
—————
— — ↕◊ ↕ —
— — ↕◊ ↕◊ —
— — ↕◊ ↕ ↕
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
BD ^dd 5
CD hh ll 6
DD ee ff 7
ED ^ff 6
FD
5
A6 ii 2
B6 ^dd 3
C6 hh ll 4
D6 ee ff 5
E6 ^ff 4
F6
3
AE ii 2
BE ^dd 3
CE hh ll 4
DE ee ff 5
EE ^ff 4
FE
3
38 ^dd 5
48
3
58
3
68 ff 6
78
5
0
b7
C
b0
DIR 34 ^dd 5
INH 44
3
— — 0 ↕ ↕ INH 54
3
IX1 64 ff 6
IX 74
5
Unsigned Multiply
Negate Byte (Two’s Complement)
No Operation
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
X : A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
A ← (A) ∨ (M)
C
b7
b0
0 — — — 0 INH 42
11
DIR 30 ^dd 5
INH 40
3
— — ↕◊ ↕ ↕ INH 50
3
IX1 60 _ff 6
IX 70
5
— — — — — INH 9D
2
IMM AA ii 2
DIR BA dd 3
— — ↕◊ ↕ —
EXT
IX2
CA ^{hh ll} 4
DA ee ff 5
IX1 EA ^ff 4
IX FA
3
DIR 39 ^dd 5
INH 49
3
— — ↕◊ ↕ ↕ INH 59
3
IX1 69 ff 6
IX 79
5
MC68HC(8)05PV8/A — Rev. 1.9
CPU and Instruction Set
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Technical Data