MC68HC05PV8 Datasheet, PDF (86/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
backup for the COP system. Because the COP needs a clock to function
it is disabled when the clock stops. Therefore, the clock monitor system
can detect clock failures not detected by the COP system.
Semiconductor wafer processing causes variations of the RC timeout
values between individual devices. A processor clock frequency below
10 KHz is detected as a clock monitor error. A processor clock frequency
of 400 KHz or more prevents clock monitor errors. Using the clock
monitor when the processor clock is below 400 KHz is not
recommended.
The oscillator used for deriving the system clock can be determined by
the RCON Bit in the interrupt status register.
$0029 Bit 7
6
5
4
3
2
1
Bit 0
Read: RCON PC4CL
0
0
0
HTIF HVIF LVIF
Write:
Reset: U
0
0
0
0
0
0
0
Figure 5-4 Interrupt Status Register (INTSR)
5.14.1 Clock Monitor in STOP mode
If STOP mode is entered, the clock monitor function is frozen. If the
device is woken from STOP mode, it continues to use the same oscillator
as before entering STOP. For the STOP mode recovery time of 4064
clock cycles, the clock monitor function is also suspended. If the device
uses an external oscillator before entering STOP mode and this
oscillator breaks during STOP, the device will no longer restart.
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
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