MC68HC05PV8 Datasheet, PDF (70/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
4.4 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner as shown in Figure 4-1. A low level input
on the RESET pin or internally generated RST signal causes the
program to vector to its starting address which is specified by the
contents of memory locations $3FFE and $3FFF. The I-bit in the
condition code register is also set. The MCU is configured to a known
state during this type of reset as described in Section 5. Resets.
4.5 Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt since
it is executed regardless of the state of the I-bit in the CCR. If the I-bit is
zero (interrupts enabled), the SWI instruction executes after interrupts
which were pending before the SWI was fetched, or before interrupts
generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of memory locations $3FFC and
$3FFD.
4.6 Hardware Interrupts
All hardware interrupts except RESET are maskable by the I-bit in the
CCR. If the I-bit is set, all hardware interrupts (internal and external) are
disabled. Clearing the I-bit enables the hardware interrupts. There are
two types of hardware interrupts which are explained in the following
sections.
4.7 External Interrupt (IRQ)
If the interrupt mask bit (I-bit) of the CCR has been cleared and the
interrupt enable bit is set (INTE bit) and the signal of the external
interrupt pin (IRQ) satisfies the condition selected by the option control
bits (INTP and INTN), then the external interrupt is recognized. INTE,
INTP and INTN are all bits contained in the system control register
located at $000A. When the interrupt is recognized, the current state of
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
Interrupts
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