MC68HC05PV8 Datasheet, PDF (71/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
Interrupts
External Interrupt (IRQ)
the CPU is pushed onto the stack and the I-bit is set. This masks further
interrupts until the present one is serviced. The interrupt service routine
address is specified by the contents of memory locations $3FFA and
$3FFB.
$000A
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
WCP
POR INTP INTN INTE WCOP
FPIE
NA
0
0
0
0
0
0
Figure 4-2 System Control Register (SYSCTRL)
Bit 0
FPICLK
0
INTP, INTN – External interrupt sensitivity options
These two bits allow the user to select which edge of the IRQ pin is
sensitive as shown in Table 4-1. Both bits can be written only while
the I-bit is set, and are cleared by power-on or external reset.
Therefore the device is initialized with negative edge and low level
sensitivity.
INTP
0
0
1
1
Table 4-2 IRQ sensitivity
INTN
0
1
0
1
IRQ sensitivity
Negative edge and low level
sensitive
Negative edge only
Positive edge only
Positive and negative edge
sensitive
INTE – External interrupt enable
1 = External interrupt function (IRQ) enabled.
0 = External interrupt function (IRQ) disabled.
The INTE bit can be written to only while the I-bit is set, and is set by
power-on or external reset, thus enabling the external interrupt function.
MC68HC(8)05PV8/A — Rev. 1.9
Interrupts
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Technical Data