MC68HC05PV8 Datasheet, PDF (151/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
Pulse Width Modulator
Registers
PRA3, PRA2, PRA1, PRA0 – PWM Clock Rate Bits
These bits select the input clock rate f_PWM. For exact values see
Table 11-1.
The PWM clock rate bits are not latched until the end of conversion.
They affect the PWM output immediately. For proper operation these
control bits must not be changed during conversion.
PRA3:PRA0
0000
0001
0010
0011
0100
0101
0110
0111
Table 11-1 PWM Clock Rate
f_PWM
f_osc
f_osc/1.5
f_osc/2
f_osc/3
f_osc/4
f_osc/6
f_osc/8
f_osc/12
PRA3:PRA0
1000
1001
1010
1011
1100
1101
1110
1111
f_PWM
f_osc/16
f_osc/24
f_osc/32
f_osc/48
f_osc/64
f_osc/96
f_osc/128
f_osc/192
11.4.2 PWM Data Register
The PWM system has an 8-bit data register that holds the duty cycle for
the PWM output. This register can be changed at any time. When the
PWMDAT register is updated, the programmed value, as well as the
POL bit, take effect in the following conversion cycle. Note that if the
contents of PWMDAT are higher than the contents of PWMPR the
output will be permanently switched to the passive state (i.e. the same
result as PWMDAT = $00).
$002E Bit 7
6
5
4
3
2
1
Bit 0
Read:
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 11-5 PWM Data Register (PWMDAT)
MC68HC(8)05PV8/A — Rev. 1.9
Pulse Width Modulator
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Technical Data