MC68HC05PV8 Datasheet, PDF (82/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
5.7 Computer Operating Properly Reset (COPR)
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to time-out, an internal reset is
generated to reset the MCU. Regardless of an internal or external reset,
the MCU comes out of a COP reset according to the pin conditions that
determine mode selection.
The COP reset function is enabled or disabled by the MOR[COPE] bit
and is verified during production testing.
The COP watchdog reset activates the internal pull-down device
connected to the RESET pin.
The window COP function can be enabled via the WCOP bit in the
system control register. This bit is a write once bit, e.g. the WCOP
feature stays enabled until the next system reset. In case of WCOP bit
enabled, the COP timer is only reset when the write to the COPEN bit in
the mask option register occurs in the second half of the COP watchdog
time. A write in the first half causes a system reset with the COPR bit set.
The phase of the COP timer can be monitored via the WCP (window
COP phase) in the system control register. A 0 indicates that writing to
the MOR bit causes system reset. A 1 indicates that writing to the MOR
bit causes a reset of the COP timer cycle.
5.7.1 Resetting the COP
A COP reset is prevented by writing a 0 to the COPR bit. This action
resets the counter and begin the time-out period again. The COPR bit is
bit 0 of address $3FF0. A read of address $3FF0 returns user data
programmed at that location.
5.7.2 COP During WAIT Mode
The COP continues to operate normally during WAIT mode. The system
should be configured to pull the device out of WAIT mode periodically
and reset the COP by writing to the COPR bit to prevent a COP reset.
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
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