MC68HC05PV8 Datasheet, PDF (170/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Technical Data
Freescale Semiconductor, Inc.
PB0
PB1
PB2
PB3
PA0-3
AS
A0–3
RW
DEN
CS
D0–3
Figure 15-1 Basic Fast Peripheral Interface Timing
The basic timing as shown in Figure 15-1 is similar to the timing used on
the HC11 parts in expanded multiplex mode. At the falling edge of the
address strobe signal (AS/PB0) the addresses on PA0–3, the read/write
signal (RW/PB1) and the chip select (CS/PB3) signal are valid. A high
DEN/PB2 signal indicates that data are driven on the bus in CPU write
cycles or that the peripheral IC can drive data in read cycles. Whenever
the FPICLK bit in the system control register is set the signals become
only active when the range from $0030–$003F is addressed by the CPU
thus significantly reducing electromagnetic noise.
When using the A/D converter in conjunction with the fast peripheral
interface the VRLEN bit of port A configuration register must be cleared.
See 7.4.4 Port A Configuration Register.
Technical Data
MC68HC(8)05PV8/A — Rev. 1.9
Fast Parallel Interface
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