MC68HC05PV8 Datasheet, PDF (139/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
Analog to Digital Converter
A/D Operation
10.4 A/D Operation
The A/D is an 8-bit successive approximation register (SAR) type A/D
converter with continuous conversion per given channel. The result of a
conversion is loaded into the read-only result data register and a
conversion complete flag COCO is set in the A/D status/control register.
Any write to the A/D status/control register will abort the current
conversion, reset the conversion complete flag and start a new
conversion on the selected channel.
At power-on or external reset both the ADRC and ADON bits are
cleared. Thus the A/D is disabled.
Each conversion takes 32 clock cycles which must be at a frequency
equal to or greater than 1 MHz.
A multiplexer allows the single A/D converter to select one of six external
analog signals two internal signal sources and three internal reference
sources.
10.5 Internal and Master Oscillator
If the MCU bus (E clock) frequency is less than 1.0 MHz, an internal RC
oscillator (nominally 1.5 MHz) must be used for the A/D conversion
clock. This selection is made by setting the ADRC bit in the A/D status
and control register to 1.
When the internal RC oscillator is being used as the conversion clock
three limitations apply:
1. The conversion complete flag (COCO) must be used to determine
when a conversion sequence has been completed, due to the
frequency tolerance of the RC oscillator and its asynchronism with
regard to the MCU bus clock.
2. The conversion process runs at the nominal 1.5 MHz rate but the
conversion results must be transferred to the MCU result registers
synchronously with the MCU bus clock so conversion time is
limited to a maximum of one channel per bus cycle.
MC68HC(8)05PV8/A — Rev. 1.9
Analog to Digital Converter
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Technical Data