MC68HC05PV8 Datasheet, PDF (85/196 Pages) Freescale Semiconductor, Inc – Techinal Data - rev 1.9

Freescale Semiconductor, Inc.
Resets
High Voltage Reset
5.11 High Voltage Reset
The internal high voltage (HVR) reset is generated when the supply
voltage V_SUP rises above the high voltage reset threshold V_HVRON. This
condition remains active until the supply voltage falls below the threshold
V_HVROFF.
This reset can be disabled by using a mask option.
5.12 Low Voltage Reset
The internal low voltage (LVR) reset is generated when the supply
voltage V_DD falls below the low voltage threshold V_LVRON. This condition
remains active until the voltage rises above the threshold V_LVROFF or a
proper power-on sequence occurs.
5.13 Operation in STOP and WAIT Mode
If enabled, all reset sources remain active during STOP and WAIT. Any
reset source can bring the MCU out of STOP or WAIT modes.
Since no instructions are executed in WAIT or STOP mode the illegal
address reset and the stop disabled reset cannot become active in
STOP or WAIT mode.
Since the core timer is not active in STOP mode, the COP reset cannot
become active in STOP mode.
On 68HC05PV8A, generation of HVR and HTR are suppressed if the
ultra low power mode is selected by setting the ULPM bit.
5.14 Clock Monitor Reset (CMR)
The clock monitor reset is based on an internal RC time delay. If no MCU
clock edges are detected within this RC time delay, the clock monitor can
optionally generate a system reset. The system clock is then
automatically switched to an on-chip RC oscillator. The clock monitor
function is enabled via a mask option bit. Clock monitor is used as a
MC68HC(8)05PV8/A — Rev. 1.9
Resets
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Technical Data